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1 tm HIP6006 buck and synchronous-rec tifier pulse-width modulator (pwm) controller the HIP6006 provides complete control and protection for a dc-dc converter optimized for high-performance microprocessor applications. it is designed to drive two n channel mosfets in a synchronous-rectified buck topology. the HIP6006 integrates all of the control, output adjustment, monitoring and protection functions into a single package. the output voltage of the converter can be precisely regulated to as low as 1.27v, with a maximum tolerance of 1% over temperature and line voltage variations. the HIP6006 provides simple, single feedback loop, voltage-mode control with fast transient response. it incl udes a 200khz free- running triangle-wave os cillator that is adjustable from below 50khz to over 1mhz. the error amplifier features a 15mhz gain-bandwidth product and 6v/ s slew rate which enables high c onverter bandwidth for fast transient performance. the resulting pwm duty ratio ranges from 0% to 100%. the HIP6006 protects against over-current conditions by inhibiting pwm operation. the HIP6006 monitors the current by using the r ds(on) of the upper mosfet which e liminates the need for a current sensing resistor. pinout HIP6006 (soic, tssop) top view features ? drives two n-channel mosfets operates from +5v or +12v input simple single-loop control design - voltage-mode pwm control fast transient response - high-bandwidth error amplifier - full 0% to 100% duty ratio excellent output voltage regulation - 1.27v internal reference - 1% over line voltage and tem perature over-current fault monitor - does not require extra current sensing element - uses mosfets r ds(on) small converter size - constant frequency operation - 200khz free-running oscillator programmable from 50khz to over 1mhz 14 pin, soic and tssop package applications power supply for pentium?, pentium pro, powerpc? and alpha? microprocessors high-power 5v to 3.xv dc-dc regulators low-voltage distributed power supplies 8 9 10 11 12 13 14 7 6 5 4 3 2 1 ocset ss en comp fb rt vcc lgate pgnd boot ugate phase gnd pvcc ordering information part number temp. range ( o c) package pkg. no. HIP6006cb 0 to 70 14 ld soic m14.15 HIP6006cv 0 to 70 14 ld tssop m14.173 HIP6006cb-t 0 to 70 14 ld soic) (t&r) m14.15 HIP6006cv-t 0 to 70 14 ld tssop (t&r) m14.173 data sheet april 2001 file number 4306.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil amer icas inc. copyright ? intersil americas inc. 2001, all rights reserved powerpc? is a trademark of ibm. alpha? is a trademark of digital equipment corporation. pentium? is a registered trademark of intel corporation.
2 typical application block diagram 12v +v o pgnd HIP6006 rt fb comp ss gnd osc lgate ugate ocset phase boot en vcc +5v or +12v pvcc +12v monitor and protection ref + - + - oscillator soft- start power-on reset (por) inhibit pwm comparator error amp vcc ss pwm rt gnd ocset fb comp en 1.27 vref over- current gate control logic boot ugate lgate phase pgnd 200 a pvcc 10 a 4v reference + - + - + - HIP6006
3 absolute maximum ratings thermal information supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15.0v boot voltage, v boot - v phase . . . . . . . . . . . . . . . . . . . . . . +15.0v input, output or i/o voltage . . . . . . . . . . . . gnd -0.3v to v cc +0.3v esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .class 2 operating conditions supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . +12v 10% ambient temperature range . . . . . . . . . . . . . . . . . . . . . 0 o c to 70 o c junction temperature range. . . . . . . . . . . . . . . . . . . . 0 o c to 125 o c thermal resistance (typical, note 1) ja ( o c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 tssop package . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range. . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300 o c (lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o n ly rating and operation of the device at these or any other c onditions above those indicated in the operat ional sections of this specification is not impl ied. note: 1. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 f or d e t a i l s . electrical specifications recommended operating conditions, unless otherwise noted parameter symbol test conditions min typ max units vcc supply current nominal supply i cc en = v cc ; ugate and lgate open - 5 - ma shutdown supply en = 0v - 50 100 a power-on reset rising v cc threshold v ocset = 4.5vdc - - 10.4 v falling v cc threshold v ocset = 4.5vdc 8.2 - - v enable - input threshold voltage v ocset = 4.5vdc 0.8 - 2.0 v rising v ocset threshold -1.27- v oscillator free running frequency r t = open, v cc = 12 185 200 215 khz total variation 6k ? < r t to gnd < 200k ? -15 - +15 % ramp amplitude ? v osc r t = open - 1.9 - v p-p reference reference voltage 1.258 1.270 1.282 v error amplifier dc gain -88- db gain-bandwidth product gbw - 15 - mhz slew rate sr comp = 10pf - 6 - v/ s gate drivers upper gate source i ugate v boot - v phase = 12v, v ugate = 6v 350 500 - ma upper gate sink r ugate i lgate = 0.3a - 5.5 10 ? lower gate source i lgate v cc = 12v, v lgate = 6v 300 450 - ma lower gate sink r lgate i lgate = 0.3a - 3.5 6.5 ? protection ocset current source i ocset v ocset = 4.5vdc 170 200 230 a soft start current i ss -10- a HIP6006
4 functional pin description rt (pin 1) this pin provides oscillator switching fre quency adjustment. by placing a resistor (r t ) from this pin to gnd, the nominal 200khz switching frequency is increased a ccording to the following equation: conversely, connecting a pull-up resistor (r t ) from this pin to v cc reduces the switching frequency according to the following equation.: ocset (pin 2) connect a resistor (r ocset ) from this pin to the drain of the upper mosfet. r ocset , an internal 200 a current source (i ocs ), and the upper mo sfet on-resistance (r ds(on) ) set the converter over-current (oc) trip point according to the following equation: an over-current trip cycles the soft-start funct ion. ss (pin 3) connect a capacitor from this pin to ground. this capacitor, along with an internal 10 a current source, sets the soft- start interval of the converter. comp (pin 4) and fb (pin 5) comp and fb are the available ex ternal pins of the e rror amplifier. the fb pin is the inverting input of the error amplifier and the comp pin is the error amplifier output. these pins are used to compensate the volt age-control feedback loop of the converter. en (pin 6) this pin is the open- collector enable pin. pull this pin below 1v to disable the converter. in shutdown, the soft start pin is discharged and the ugate and lgate pins are held low. gnd (pin 7) signal ground for the ic. all voltage levels are measured with respect to this pin. phase (pin 8) connect the phase pin to the upper mosfet source. this pin is used to monitor the voltage drop across the mosfet for over-current protection. this pin also provides the return path for the upper gate drive. ugate (pin 9) connect ugate to the upper mo sfet gate. this pin provides the gate drive for the upper mosfet. boot (pin 10) this pin provides bias voltage to the upper mosfet driver. a bootstrap circuit may be used to create a boot volt age suitable to drive a standard n-channel mosfet. pgnd (pin 11) this is the power ground connection. tie the lower mosfet source to this pin. typical performance curves figure 1. r t resistance vs frequency figure 2. bias supply current vs frequency 10 100 1000 switching frequency (khz) resistance (k ? ? ? ? ) 10 100 1000 r t pullup to +12v r t pulldown to v ss 100 200 300 400 500 600 700 800 900 1000 80 70 60 50 40 30 20 10 0 i vcc (ma) switching frequency (khz) c gate = 1000pf c gate = 3300pf c gate = 10pf 8 9 10 11 12 13 14 7 6 5 4 3 2 1 ocset ss en comp fb rt vcc lgate pgnd boot ugate phase gnd pvcc fs 200khz 510 6 ? r t k ? () -------------------- - + (r t to gnd) fs 200khz 410 7 ? r t k ? () -------------------- - ? (r t to 12v) i peak i ocs r ocset ? r ds on () ------------------------------------------- - = HIP6006
5 lgate (pin 12) connect lgate to the lower mosfet gate. this pin provides the gate drive for the lower mosfet. pvcc (pin 13) provide a bias supply for the lower gate drive to this pin . vcc (pin 14) provide a 12v bias supply for the chip to this pin. functional description initialization the HIP6006 automatically initializes upon receipt of power. special sequencing of the i nput supplies is not necessary. the power-on reset (por) function continually monitors the input supply voltages and the enable (en) pin. the por monitors the bias voltage at the vcc pin and the input voltage (v in ) on the ocset pin. the level on ocset is equal to v in less a fixed voltage drop (see over-current protection). with the en pin held to v cc , the por function initiates soft start operation after both input supply voltages exceed their por thresholds. for operation with a single +12v power source, v in and v cc are equivalent and the +12v power source must exceed the rising v cc threshold before por initiates operation. the power-on reset (por) function inhibits operation with the chip disabled (en pin low). with both input supplies above their por thresholds, transitioning the en pin high initiates a soft start interval. soft start the por function initiates the soft start sequence. an internal 10 a current source charges an external capacitor (c ss ) on the ss pin to 4v. soft start clamps the error amplifier output (comp pin) and reference input (+ terminal of error amp) to the ss pin voltage. figure 3 shows the soft start interval with c ss = 0.1 f. initially the clamp on the error amplifier (comp pin) controls the converter?s output voltage. at t1 in figure 3, the ss voltage reaches the valley of the oscillator?s triangle wave. the oscillator?s triangular waveform is compared to the ramping error amplifier voltage. this generates phase pulses of increasing width that charge the output capacitor(s). this interval of increasing pulse width continues to t2. with sufficient output voltage, the clamp on the reference input controls the output voltage. this is the interval between t2 and t3 in figure 3. at t3 the ss voltage exceeds the reference voltage and the output voltage is in regulation. this method provides a rapid and controlled output voltage rise. over-current protection the over-current function protects the converter from a shorted output by us ing the upper mosfets on-resistance, r ds(on) to monitor the current. this method enhances the converter?s efficiency and reduces cost by e liminat ing a current sensing resistor. the over-current function cycles the soft-start function in a hiccup mode to provide fault protection. a resistor (r ocset ) programs the over-current trip level. an internal 200 a (typical) current sink develops a voltage across r ocset that is reference to v in . when the voltage across the upper mosfet (also referenced to v in ) exceeds the voltage across r ocset , the over-current function initiates a soft- start sequence. the soft-start function discharges c ss with a 10 a current sink and inhibits pwm operation. the soft- start function recharges c ss , and pwm operation resumes with the error amplifier clamped to the ss voltage. should an overload occur while recharging c ss , the s oft start function inhibits pwm operation while fully charging c ss to 4v to time (5ms/div) soft-start (1v/div) 0v 0v t1 t2 t3 output (1v/div) voltage figure 3. soft-start interval output inductor soft-start 0a 0v time (20ms/div) 5a 10a 15a 2v 4v figure 4. over-current operation HIP6006
6 complete its cycle. figure 4 shows this operation with an overload condition. note that the inductor current increases to over 15a during the c ss charging interval and causes an over-current trip. the converter dissipates very little power with this method. the measured input power for the conditions of figure 4 is 2.5w. the over-current function w ill trip at a peak inductor cur rent (i peak) determined by: where i ocset is the internal ocset current source (200 a - typical). the oc trip point varies m ainly due to the mosfets r ds(on) variations. to avoid over-cur rent tripping in the normal operating load range, find the r ocset resistor from the equation above with: 1. the maximum r ds(on) at the highest junction temperature. 2. the minimum i ocset from the specification table. 3. determine , where ? i is the output inductor ripple current. for an equat ion for the ripple current see the section under component guidelines titled ?output inductor selection?. a small ceramic capacitor should be placed in parallel with r ocset to smooth the voltage across r ocset in the presence of switching noise on the input volt age. application guidelines layout considerations as in any high fr equency switching converter, layout is very important. switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. these interconnecting impedances should be minimized by using wide, short printed circuit traces. the critical components should be loca ted as close together as possible using ground plane construction or single point grounding. figure 5 shows the critical power components of the converter. to minimize the voltage overshoot the interconnecting wires indicated by heavy lines should be part of ground or power plane in a printed circuit board. the components shown in figure 6 should be located as close together as possible. please note that the capacitors c in and c o each represent numerous physical capacitors. locate the HIP6006 within 3 inches of the mosfets, q1 and q2. the circuit traces for the mosfets? gate and source connections from the HIP6006 must be sized to handle up to 1a peak current. figure 6 shows the circuit traces that r equire additional layout consideration. use single point and ground plane construction for the circuits shown. minimize any leakage current paths on the ss pin and locate the capacitor, c ss close to the ss pin because the internal current source is only 10 a. provide local v cc decoupling between vcc and gnd pins. locate the capacitor, c boot as close as practical to the boot and phase pins. feedback compensation figure 7 highlights the voltage-mode control loop for a synchronous-rectified buck converter. the output voltage (vout) is regulated to the reference voltage level. the e rror amplifier (error amp) output (v e/a ) is compared with the oscillator (osc) triangular wave to prov ide a pulse-w idth modulated (pwm) wave with an amplitude of v in at the phase node. the pwm wave is smoothed by the output filter (l o and c o ). the modulator transfer function is the small-signal transfer function of vout/v e/a . this function is dominated by a dc gain and the output filter (l o and c o ), with a double pole break frequency at f lc and a zero at f esr . the dc gain of the modulator is simply the input voltage (v in ) divided by the peak-to-peak oscillator voltage ? v osc . i peak i ocset r ocset ? r ds on () --------------------------------------------------- = i peak for i peak i out max () ? i () 2 ? + > pgnd l o c o lgate ugate phase q1 q2 d2 figure 5. printed circuit board power and ground planes or islands v in v out return HIP6006 c in load figure 6. printed circuit board small signal layout guidelines +12v HIP6006 ss gnd vcc boot d1 l o c o v out load q1 q2 phase +v in c boot c vcc c ss HIP6006
7 modulator break frequency equations the compensation network consists of the error am plifier (internal to the HIP6006) and the impedance networks z in and z fb . the goal of the compensation network is to provide a closed loop transfer function with the highest 0db crossing frequency (f 0db ) and adequate phase margin. phase margin is the difference between the closed loop phase at f 0db and 180 o . the equations below relate the compensation network?s poles, zeros and gain to the components (r1, r2, r3, c1, c2, and c3) in figure 8. use these guidelines for locating the poles and zeros of the compensation network: compensation break frequency equations 1. pick gain (r2/r1) for desired converter bandwidth 2. place 1 st zero below filter?s double pole (~75% f lc ) 3. place 2 nd zero at filter?s double pole 4. place 1 st pole at the esr zero 5. place 2 nd pole at half the switching frequency 6. check gain against error amplifier?s open- loop gain 7. estimate phase margin - repeat if necessary figure 8 shows an asymptotic plot of the dc-dc converter?s gain vs frequency. the actual modulator gain has a high gain peak do to the high q factor of the output filter and is not shown in figure 8. using the above guidelines should give a compensation gain similar to the curve plotted. the open loop error amplifier gain bounds the compensation gain. check the compensation gain at f p2 with the capabilities of the error amplifier. the closed loop gain is constructed on the log-log graph of figure 8 by adding the modulator gain (in db) to the compensation gain (in db). this is equivalent to m ultiply ing the modulator transfer function to the compensation transfer function and plotting the gain. the compensation gain uses external impedance netw orks z fb and z in to provide a stable, high bandwidth (bw) overall loop. a stable control loop has a gain crossing with - 20db/decade slope and a phase margin greater than 45 o . include worst case component variations when determining phase margin. component selection guidelines output capacitor selection an output capacitor is required to filter the output and supply the load transient current. the filtering requirements are a function of the switching frequency and the ripple current. the load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. these requirements are generally met with a mix of capacitors and careful layout. figure 7. voltage - mode buck converter compensation design v out osc reference l o c o esr v in ? v osc error amp pwm driver (parasitic) - ref r1 r3 r2 c3 c2 c1 comp v out fb z fb HIP6006 z in comparator driver detailed compensation components phase v e/a + - + - z in z fb + f lc 1 2 l o c o ? ? -------------------------------------- - = f esr 1 2 esr c o ? () ? --------------------------------------------- = f z1 1 2 r ? 2c1 ? ---------------------------------- = f z2 1 2 r1 r3 + () c3 ? ? ----------------------------------------------------- - = f p1 1 2 r2 ? c1 c2 ? c1 c2 + ---------------------- ?? ?? ? ------------------------------------------------------ - = f p2 = 1 2 r3 c3 ? ? ---------------------------------- 100 80 60 40 20 0 -20 -40 -60 f p1 f z2 10m 1m 100k 10k 1k 100 10 open loop error amp gain f z1 f p2 f lc f esr compensation gain (db) frequency (hz) gain 20log (v in / ? v osc ) modulator gain 20log (r2/r1) closed loop gain figure 8. asymptotic bode plot of converter gain HIP6006
8 modern microprocessors produce transient load rates above 1a/ns. high frequency capacitors initially s upply the transient and slow the current load rate seen by the bulk capacitors. the bulk filter c apacitor val ues are generally determined by the esr (effective series resistan ce) and voltage rating requirements rather than actual capacitance requirements. high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. consult with the manufacturer of the load on specific decoupling requirements. for example, intel recommends that the high frequency decoupling for the pentium pro be composed of at least forty (40) 1.0 f ceramic capacitors in the 1206 surface-mount package. use only specialized low-esr capacitors intended for switching-regulator applications for the bulk capacitors. the bulk capacitor?s esr will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. an aluminum electrolytic capacitor's esr value is related to the case size with lower esr available in larger case sizes. however, the equivalent series inductance (esl) of these capacitors increases with c ase size and can reduce the usefulness of the capacitor to high slew-rate transient loading. unfortunately, esl is not a specified parameter. work with your capacitor supplier and measure the capacitor?s impedance with frequency to select a suitable component. in most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. output inductor selection the output inductor is selected to meet the output voltage ripple requirements and minimize the converter?s response time to the load transient. the inductor value determines the converter?s ripple current and the ripple voltage is a function of the ripple current. the ripple voltage and current are approximated by the following e quations: increasing the value of inductance reduces the ripple current and voltage. however, the large i nductance values reduce the converter?s response time to a load transient. one of the parameters limiting the converter?s response to a load transient is the time required to change the inductor current. given a sufficiently fast control loop design, the HIP6006 will provide either 0% or 100% duty cycle in response to a load transient. the response time is the time required to slew the inductor current from an initial current value to the transient current level. during this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. minimizing the response time can minimize the output capacitance required. the response time to a transient is different for the application of load and the removal of load. the following equations give the approximate response time interval for application and remo val of a transient load: where: i tran is the transient load current step, t rise is the response time to the application of load, and t fall is the response time to the removal of load. with a +5v input source, the worst case response time can be either at the application or removal of load and depen dent upon the output voltage setting. be sure to check both of these equations at the minimum and max imum output levels for the worst case response time. input capacitor selection use a mix of input bypass capacitors to control the voltage overshoot across the mosfets. use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time q1 turns on. place the small ceramic capacitors physically close to the mosfets and between the drain of q1 and the source of q2. the important parameters for the bulk input capacitor are the voltage rating and the rms current rating. for reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. the rms current rating r equirement for the input capacitor of a buck regulator is approximately 1/2 the dc load current. for a through hole design, several electrolytic c apacitors (panasonic hfq series or nichicon pl series or sanyo mv- gx or equivalent) may be needed. for surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge curr ent rating. these capacitors must be capable of h andling the surge-current at power-up. the tps series available from avx, and the 593d series from spr ague are both surge current tested. mosfet selection/considerations the HIP6006 requires 2 n-channel power mosfets. these should be selected based upon r ds(on) , gate supply requirements, and thermal management requirements. in high-current applications, the mosfet power dissipation, package selection and heatsink are the dominant design factors. the power dissipation inc ludes two loss components; conduction loss and switching loss. the ? v out = ? i x esr ? i = v in - v out fs x l ------------------------------- - v out v in --------------- - ? t fall l o i tran v out ------------------------------ - = t rise l o i tran v in v out ? ------------------------------- - = HIP6006
9 conduction losses are the largest component of power dissipation for both the upper and the lower mosfets. these losses are distributed between the two mosfets according to duty factor (see the equations below). only the upper mosfet has switching losses, since the schottky rectifier clamps the switching node before the synchronous rectifier turns on. these equati ons assume li near vol tage-current transitions and do not adequately model power loss due the reverse- recovery of the lower mosfets body diode. the gate-charge losses are diss ipated by the HIP6006 and d on't heat the mosfets. however, large gate-charge increases the switching interval, t sw which increases the upper mosfet switching losses. ensure that both mosfets are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. a separate heatsink may be necessary depending upon mo sfet power, package type, ambient temperature and air flow. standard-gate mosfets are normally recommended for use with the HIP6006. however, logic-level gate mosfets can be used under special circumstances. the input voltage, upper gate drive level, and the mosfets absolute ga te-to- source voltage rating determine whether logic-level mosfets are appropriate. figure 9 shows the upper gate drive (boot pin) s upplied by a bootstrap circuit from v cc . the boot capacitor, c boot develops a floating supply voltage referenced to the phase pin. this supply is refreshed each cycle to a voltage of v cc less the boot diode drop (v d ) when the lower mosfet, q2 turns on. a logic-level mosfet can only be used for q1 if the mosfets absolute gate-to-source voltage rating exceeds the maximum voltage applied to v cc . for q2, a logic-level mosfet can be used if its absolute gate-to- source voltage rating exc eeds the maximum voltage applied to pvcc. figure 10 shows the upper gate drive supplied by a di rect connection to v cc . this option should only be used in converter systems where the main input voltage is +5 vdc or less. the peak upper gate-to-source voltage is approximately vcc less the input supply. for +5v main power and +12 vdc for the bias, the gate-to-source volt age of q1 is 7v. a logic-level mosfet is a good choice for q1 and a logic- level mosfet can be used for q2 if its absolute gate-to-source voltage rating exceeds the maximum voltage applied to pvcc. schottky selection rectifier d2 is a clamp that catches the negative inductor swing during the dead time between turning off the lower mosfet and turning on the upper mosfet. the diode must be a schottky type to prevent the lossy parasitic mosfet body diode from conducting. it is acceptable to omit the diode and let the body diode of the lower mosfet clamp the negative inductor swing, but efficiency will drop one or two percent as a result. the diode's rated reverse breakdown voltage must be greater than the maximum input voltage. p upper = i o 2 x r ds(on) x d + 1 2 io x v in x t sw x fs p lower = i o 2 x r ds(on) x (1 - d) where: d is the duty cycle = v o / v in , t sw is the switching interval, and fs is the switching frequency. +12v pgnd HIP6006 gnd lgate ugate phase boot vcc +5v or +12v figure 9. upper gate drive - bootstrap option note: v g-s v cc - v d note: v g-s pvcc c boot d boot q1 q2 pvcc +5v or +12v d2 + - v d + - +12v pgnd lgate ugate phase boot vcc +5v or less figure 10. upper gate drive - direct v cc drive option note: v g-s v cc - 5v note: v g-s pvcc q1 q2 pvcc +5v or +12v d2 HIP6006 gnd + - HIP6006
10 HIP6006 dc-dc converter application circuit the figure below shows an application circuit of a dc-dc converter for a microprocessor application. detailed information on the circuit, including a comp lete bill-of- materials and circuit board description, can be found in application note an9 722. see intersil?s home page on the web: www.intersil.com. HIP6006 rt fb comp ss ref - + gnd + - osc vcc vin c1-3 l1 c6-9 0.1 f 2x 1 f 0.1 f 1 f 15k 1k 3x 680 f 4x 1000 f ugate ocset phase boot spare cr1 q1 3.01k 1000pf cr2 c13 r1 r3 r4 c15 r5 c14 c12 c17-18 c19 r6 c20 4148 u1 rtn 12vcc 14 2 10 9 8 7 4 5 1 3 spare pgnd lgate 12 11 pvcc 13 jp1 q2 1206 1206 mbr 340 v out rtn enable r2 1k comp tp1 phase tp2 6 r7 10k monitor and protection + - + - c16 0.01 f 33pf spare component selection notes: c1-c3 - 3 each 680 f 25w vdc, sanyo mv-gx or equivalent c6-c9 - 4 each 1000 f 6.3w vdc, sanyo mv-gx or equivalent l1 - core: micrometals t50-52b; winding: 10 turns of 17awg cr1 - 1n4148 or equivalent cr2 - 3a, 40v schottky, motorola mbr340 or equivalent q1, q2 - intersil mosfet; rfp25n05 figure 11. dc-dc converter application circuit HIP6006
11 HIP6006 thin shrink small outline plastic packages (tssop) index area e1 d n 123 -b- 0.10(0.004) c a m bs e -a- b m -c- a1 a seating plane 0.10(0.004) c e 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 notes: 1. these package dimensions are within allowable dimensions of jedec mo-153-ac, issue e. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not include interlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimen- sion at maximum material condition. minimum space between protru- sion and adjacent lead is 0.07mm (0.0027 inch). 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. (angles in degrees) 0.05(0.002) m14.173 14 lead thin shrink small outline plastic package symbol inches millimeters notes min max min max a - 0.047 - 1.20 - a1 0.002 0.006 0.05 0.15 - a2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - d 0.195 0.199 4.95 5.05 3 e1 0.169 0.177 4.30 4.50 4 e 0.026 bsc 0.65 bsc - e 0.246 0.256 6.25 6.50 - l 0.0177 0.0295 0.45 0.75 6 n14 147 0 o 8 o 0 o 8 o - rev. 1 6/00
12 all intersil products are manufactured, assembled and tested u tilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at website www.intersil.com/design/ quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r specifications at any time without notice. accordingly, the reader is c autioned to verify that data sheets are current before placing orders. information furnished by inte rsil is believed to be accurate and reliable. how- ever, no responsib ility is assumed by intersil or its subs idiaries for its use; nor for any infringements of patents or other ri ghts of third parties which may result from its use. no license is granted by implication or otherwise under any patent or pat ent rights of intersil or its subsidiaries. for information regarding intersil corporation and its produc ts, see web sit e www.intersil.com sales office headquarters north america intersil corporation 2401 palm bay rd., mail stop 53-204 palm bay, fl 32905 tel: (321) 724-7000 fax: (321) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil ltd. 8f-2, 96, sec. 1, chien-kuo north, taipei, taiwan 104 republic of china tel: 886-2-2515-8508 fax: 886-2-2515-8369 HIP6006 small outline plastic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not ex ceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 in ch) per side. 5. the chamfer on the body is optional. if it is not p resent, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m14.15 (jedec ms-012-ab issue c) 14 lead narrow body small outline plastic package symbol inches millimeters notes minmaxminmax a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.3367 0.3444 8.55 8.75 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n14 147 0 o 8 o 0 o 8 o - rev. 0 12/93

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